AC/DC Calc. A little more clarity.

THE MODEL COMES FIRST

AC to DC calculator

Separate an unfiltered rectifier, a capacitor-filtered supply and a downstream DC regulator. Input conventions and assumptions change with the circuit.

CALCULATE WITH A DEFINED MODEL

AC to DC converter calculator

Runs on your device

Choose rectification, filtering, or a downstream regulator stage. Each solves a different question.

Single-phase sinusoidal AC input
RMS at the rectifier input, after any transformer.
Use a datasheet operating-point assumption; 0 models ideal diodes.
Capacitor and load

Calculated result

Average DC
15.070563 V
Input sine peak
16.970563 V
Output crest
15.570563 V
Output valley
14.570563 V
Ripple p-p
1 V
Ripple p-p / average
6.6354523 %
Average load current
0.1 A
Pulse / recharge frequency
100 Hz

Vtop = max(0, √2 Vrms − nVf); ΔVpp = I / (fr C); Vavg ≈ Vtop − ΔVpp / 2

Modeled input and output over two AC cycles
Dashed: AC input. Solid blue: idealized output model, over two AC cycles. This is an explanatory waveform, not an oscilloscope measurement.
Assumptions and interpretation
  • Sinusoidal single-phase input; a fixed forward drop per conducting diode. Source impedance and diode dynamics are excluded.
  • A four-diode bridge has two forward drops per conducting path.
  • Constant-current load, linear capacitor discharge and instantaneous recharge at each crest.
  • C is converted from µF to farads. Ripple percent is peak-to-peak ripple divided by average DC, not RMS ripple factor.
  • A 20% crest-ripple guardrail limits model scope; it is not an accuracy guarantee or component rating. Source resistance, finite charging time, ESR, inrush and thermal design are excluded.

Educational estimate only. Calculations do not replace electrical design, isolation, component ratings, protection, thermal analysis or qualified engineering review. Never connect exposed experimental circuits directly to mains.

Read the calculation methodology · Ideal full-wave tool · Ideal half-wave tool

Calculation methodology

A · Basic constant-drop rectifier

For sinusoidal input, Vpk = √2 Vrms. Let D = nVf, where n = 2 for a bridge and n = 1 for half-wave or a center-tapped path. Above threshold, θ0 = asin(D/Vpk). Integrating the clipped sine over a full cycle gives Vavg = [2 Vpk cos θ0 − D(π − 2θ0)] / π for full-wave, or half this value for half-wave. If D ≥ Vpk the output is zero.

This accounts for the non-conducting interval in a fixed-drop model. It does not subtract the diode drop from an ideal average indiscriminately. The output RMS is calculated from the integral of the squared clipped waveform. The separate ideal full-wave and ideal half-wave tools retain their zero-drop scope.

B · Filtered current and resistance loads

Recharge frequency fr is f for half-wave and 2f for single-phase full-wave. For constant current, ΔVpp = I/(fr C) and Vavg ≈ Vtop − ΔVpp/2. For resistance, x = 1/(fr R C); instantaneous crest recharging followed by exponential discharge gives Vvalley = Vtop exp(−x) and Vavg = Vtop [1 − exp(−x)]/x. Average load current is Vavg/R.

Both deliberately omit source resistance, finite charging time, capacitor ESR, leakage and temperature. A peak-to-peak ripple limit of 20% of the available crest is a scope guardrail, not a guaranteed error bound. Input capacitance is µF; the engine converts to farads. Center-tapped RMS is per winding half, not end-to-end.

C · Conditional regulator-stage result

Use the minimum raw DC input, including upstream ripple valley, and a device-specific headroom requirement. If that minimum is too low, regulation is rejected. Linear/LDO power balance includes quiescent current: Ploss = (Vin − Vout)Iout + Vin Iq. For the switching stage, efficiency is supplied by you; Pin = Pout/η. Neither mode predicts current capability, stability or junction temperature.

Efficiency is undefined when input power is zero. Regulator-stage efficiency does not include upstream AC input, transformer, rectifier or filter losses. Output switching ripple is not modeled.

Checked numerical examples

  • 12 V RMS bridge, 0.7 V per diode, 50 Hz, 0.1 A and 1,000 µF: crest 15.5706 V, ripple 1 V p-p, average 15.0706 V, valley 14.5706 V.
  • Zero-drop ideal full-wave at 12 V RMS: average 10.8038 V. Half-wave average: 5.4019 V.
  • Linear stage: minimum input 12 V, output 5 V at 1 A, Iq 1 mA: output 5 W, input 12.012 W, loss 7.012 W, stage efficiency about 41.625%.

References and independent checks

Derivations are checked against independent numerical integration and boundary tests. See Hammond's topology/filter guide, TI TIDUB95 section 3.1 for capacitor charge and ripple, and TI's linear-regulator seminar for headroom, loss and efficiency context. These are model checks, not physical measurements.

For broader context, explore original circuit diagrams, formula selection, and the limits of a simple calculator.